PRELIMINARY

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

512Mb: x4, x8, x16

SDRAM

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_F.p65 Rev. F; Pub 1/03

KEY TIMING PARAMETERS

SPEED

CLOCK

ACCESS TIME

SETUP

HOLD

GRADE

FREQUENCY CL = 2* CL = 3*

TIME

-7E

143 MHz

5.4ns

1.5ns

0.8ns

-75

133 MHz

5.4ns

1.5ns

0.8ns

-7E

133 MHz

5.4ns

1.5ns

0.8ns

-75

100 MHz

6ns

1.5ns

0.8ns

128 Meg x 4

64 Meg x 8

32 Meg x 16

Configuration

32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks

Refresh Count

Row Addressing

8K (A0A12)

Bank Addressing

4 (BA0, BA1)

Column Addressing 4K (A0A9, A11, A12)

2K (A0A9, A11)

1K (A0A9)

SYNCHRONOUS
DRAM

MT48LC128M4A2 32 Meg x 4 x 4 banks
MT48LC64M8A2 16 Meg x 8 x 4 banks
MT48LC32M16A2 8 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dramds

Pin Assignment (Top View)

54-Pin TSOP

FEATURES

· PC100- and PC133-compliant
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can be

changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

· Self Refresh Mode
· 64ms, 8,192-cycle refresh
· LVTTL-compatible inputs and outputs
· Single +3.3V ±0.3V power supply

OPTIONS

MARKING

· Configurations

128 Meg x 4 (32 Meg x 4 x 4 banks)

128M4

64 Meg x 8 (16 Meg x 8 x 4 banks)

64M8

32 Meg x 16 (8 Meg x 16 x 4 banks)

32M16

· WRITE Recovery (

WR)

WR = "2 CLK"

· Plastic Package OCPL

54-pin TSOP II (400 mil)

· Timing (Cycle Time)

7.5ns @ CL = 2 (PC133)

-7E

7.5ns @ CL = 3 (PC133)

-75

· Self Refresh

Standard

None

Low power

· Operating Temperature

Commercial (0

C to +70

None

NOTE: 1. Refer to Micron Technical Note TN-48-05.

2. Off-center parting line.

Part Number Example:

MT48LC32M16A2TG-75

NOTE: The # symbol indicates signal is active LOW. A dash

() indicates x8 and x4 pin function is same as x16
pin function.

DQ0

DQ1
DQ2

VssQ

DQ3
DQ4

DQ5
DQ6

VssQ

DQ7

DQML

WE#

CAS#
RAS#

CS#

BA0
BA1

A10

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

Vss

DQ15

VssQ

DQ14
DQ13

DQ12
DQ11

VssQ

DQ10
DQ9

DQ8

Vss
NC
DQMH
CLK
CKE

A12
A11
A9
A8
A7
A6
A5
A4

Vss

x16

DQ0

DQ1

DQ2

DQ3

DQ0

NC
NC

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

NC
NC

DQ2

DQM

*CL = CAS (READ) latency

512Mb SDRAM PART NUMBERS

PART NUMBER

ARCHITECTURE

MT48LC128M4A2TG

128 Meg x 4

MT48LC64M8A2TG

64 Meg x 8

MT48LC32M16A2TG

32 Meg x 16

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_F.p65 Rev. F; Pub 1/03

512Mb: x4, x8, x16

SDRAM

PRELIMINARY

page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.

The 512Mb SDRAM uses an internal pipelined archi-

tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully ran-
dom access. Precharging one bank while accessing one of
the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.

The 512Mb SDRAM is designed to operate at 3.3V. An

auto refresh mode is provided, along with a power-sav-
ing, power-down mode. All inputs and outputs are LVTTL-
compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during a burst access.

GENERAL DESCRIPTION

The 512Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the x4's
134,217,728-bit banks is organized as 8,192 rows by 4,096
columns by 4 bits. Each of the x8's 134,217,728-bit banks
is organized as 8,192 rows by 2,048 columns by 8 bits.
Each of the x16's 134,217,728-bit banks is organized as
8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-A12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_F.p65 Rev. F; Pub 1/03

512Mb: x4, x8, x16

SDRAM

PRELIMINARY

TABLE OF CONTENTS

Functional Block Diagram 128 Meg x 4 ....................

Functional Block Diagram 64 Meg x 8 ...................

Functional Block Diagram 32 Meg x 16 .................

Pin Descriptions ...........................................................

Functional Description ...............................................

Initialization ............................................................

Mode Register ....................................................

Burst Length .................................................

Burst Type ....................................................

CAS Latency ................................................. 10
Operating Mode ........................................... 10
Write Burst Mode ......................................... 10

Commands .................................................................... 11

Truth Table 1 (Commands and DQM Operation)

............ 11

Command Inhibit ................................................... 12
No Operation (NOP) ............................................... 12
Load Mode Register ................................................ 12
Active ....................................................................... 12
Read ....................................................................... 12
Write ....................................................................... 12
Precharge ................................................................. 12
Auto Precharge ........................................................ 12
Burst Terminate ...................................................... 13
Auto Refresh ............................................................ 13
Self Refresh .............................................................. 13

Operation ...................................................................... 14

Bank/Row Activation .............................................. 14
Reads ....................................................................... 16
Writes ....................................................................... 21
Precharge ................................................................. 23
Power-Down ............................................................ 23
Clock Suspend ......................................................... 24

Burst Read/Single Write ......................................... 24
Concurrent Auto Precharge ................................... 25

Truth Table 2 (CKE)

..................................................... 27

Truth Table 3 (Current State, Same Bank)

...................... 28

Truth Table 4 (Current State, Different Bank)

................. 30

Absolute Maximum Ratings ........................................ 32
DC Electrical Characteristics and Operating

Conditions ................................................................ 32

Specifications and Conditions .............................. 32

Capacitance ................................................................... 33

AC Electrical Characteristics (Timing Table) ............ 33

Timing Waveforms

Initialize and Load Mode Register ......................... 36
Power-Down Mode ................................................. 37
Clock Suspend Mode .............................................. 38
Auto Refresh Mode ................................................. 39
Self Refresh Mode ................................................... 40
Reads

Read Without Auto Precharge ....................... 41
Read With Auto Precharge ............................. 42
Single Read Without Auto Precharge ............ 43
Single Read With Auto Precharge ................. 44
Alternating Bank Read Accesses ...................... 45
Read Full-Page Burst ...................................... 46
Read DQM Operation .................................... 47

Writes

Write Without Auto Precharge ...................... 48
Write With Auto Precharge ............................ 49
Single Write Without Auto Precharge ........... 50
Single Write With Auto Precharge ................. 51
Alternating Bank Write Accesses ..................... 52
Write Full-Page Burst ..................................... 53
Write DQM Operation .................................... 54

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